During this years EDA Consortium Annual (EDAC) CEO Forecast and Industry Vision, CEOs responded to a pre-panel question on the challenges of IC deisgn and cited ' integration' as a key issue. See Richard Goerings blog on this. The panel was comprised of :
- Edmund Cheng, President & CEO, Gradient Design Automation, Inc.
- Aart de Geus, Chairman & CEO, Synopsys, Inc.
- Walden C. Rhines, Chairman & CEO, Mentor Graphics Corporation
- Simon Segars, EVP & General Manager, Physical IP Division, ARM, Ltd
- Lip-Bu Tan, President & CEO, Cadence Design Systems. Inc.
The panel session was moderated byEd Sperling, Editor in Chief, System Level Design. On the topic of IP Integration, Sperling posed the following question :
"The world of IP people thought we would go with a Lego [assembly] approach, but it doesn't go together that easily. Will we see larger Legos?"
There were some interesting responses.
Segars responded saying that bigger Legos are inevitable and 'there are a million ways you can put your chip together and a million and one ways to get it wrong. The biggest challenge is checking to make sure it's done correctly.' The growth in SoC complexity can be seen as growth in the complexity of your building blocks (IP/Lego) as well as more of the IP.
Lip-Bu Tan's answer related complexity to the widening of the scope of the lego. IP is no longer simply an RTL view but now includes a multitude of design disciplines/domains (e.g. it now includes a software aspect) and the corresponding integration task must resolve these aspects within the fundamental goals of PPA as well as cost.
De Geus built on Tan's answer to highlight that the complexity was pushing the high-level boundaries of software and the physical boundaries of the semiconductor technlogy. He talked about some power use-case examples and the conversation then moved toward power discussions.
From what I see, growing complexity is a real challange to IP integration. From a pure data perspective - there's a lot more of it, the type of data is changing, it has to be resolved within shorter timeframes and quality cannot be compromized.
Whilst I agree with Segar's challenge of checking that integration it is done correctly and with the industry straining at the greater challenges in SoC verification complexity, I think we should also keep focused on the challange to strive to integrate correctly in the first place