DAC is just around the corner (It seems to have been lurking there since DVCon in Feb) and besides going to the usual parties, there's quite a lot to get through. For my own part I have several talks to give (luckily later in the day), mentioned below. Feel free to drop by the Duolog booth #568 for a chat:
AEIOU(VM) - Any Vowel will do!
Monday 14th June : 5pm : OVMWorld booth # 1350
This presentation highlights the emergence of the HW/SW interface as a very important target for advanced verification methodologies. However, As verification methodologies continue to evolve and innovate, there is a continuous increment and change in verification implementations. By moving to a higher level of abstraction, and modeling the HW/SW interface at this level, it is possible to ensure smooth transition to emerging and maturing verification methodologies evolve. We demonstrate that using Socrates we can, from a single source specification, generate OVM and UVM models of the HW/SW interface, leaving verification engineers free to focus on real design verification and allowing smoother transitions to new verification methodologies as they mature.
Verification Productivity : Introducing and eliminating the GNAT (Non-Aligned teams)
Wednesday 16th June : 5pm : OVMWorld booth # 1350
As software development continues to demand earlier and more robust hardware releases, this is causing an increasingly pressurized parallel development effort. Within this design environment it is crucial to ensure that teams are working efficiently together. Traditional design flows, however, are not keeping up to pace with these requirements leading to an emergence of a particular type of design bug, which we are calling the GNAT - Non aligned teams. In this presentation we identify the GNATs, show how they effect productivity and propose ways of eliminating them from the design flow.
SOCRATES - Hub for IP integration
Monday 14th,Tuesday 15th, Wednesday 16th June : 10-5pm : Duolog booth # 568
See how Socrates can be used as a hub for IP Integration. We show that through IP standardization, coherency checking and auto-generation; high-quality, single-source IP data can be used to create a wide range of design view outputs keeping design/verification - HW/SW - architecture-implementation teams in sync and ensuring the IP is integration-ready.
Ringing In and Out: Automated Creation of the SoC I/O Ring
DAC User Track, 9U.8 S
Thursday, June 17, 2010
Time: 9:00 AM — 11:00 AM
Location: 208AB
DAC User Track presentation showing automated I/O integration. This user track shows the automated creation of the I/O Ring on a complex TI multimeda SoC, including pin multiplexing, I/O cell insertion and DFT insertion. This presentation also details the use of IP-XACT within this I/O integration activity.
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