Integration Insights

CEOs identified "integration" as the key challenge in IC design

During this years EDA Consortium Annual (EDAC) CEO Forecast and Industry Vision,  CEOs responded to a pre-panel  question on the challenges of IC deisgn and cited ' integration' as a key issue.  See Richard Goerings blog on this. The panel was comprised of :

• Edmund Cheng, President & CEO, Gradient Design Automation, Inc.    
• Aart de Geus, Chairman & CEO, Synopsys, Inc.    
• Walden C. Rhines, Chairman & CEO, Mentor Graphics Corporation
• Simon Segars, EVP & General Manager, Physical IP Division, ARM, Ltd    
• Lip-Bu Tan, President & CEO, Cadence Design Systems. Inc.

The panel session was moderated byEd Sperling, Editor in Chief, System Level Design.   On the topic of IP Integration, Sperling posed the following question :

"The world of IP people thought we would go with a Lego [assembly] approach, but it doesn't go together that easily. Will we see larger Legos?"

There were some interesting responses.

Segars responded saying that bigger Legos are inevitable and 'there are a million ways you can put your chip together and a million and one ways to get it wrong. The biggest challenge is checking to make sure it's done correctly.'    The growth in SoC complexity can be seen as growth in the complexity of your building blocks (IP/Lego) as well as more of the IP.  

Lip-Bu Tan's answer related complexity to the widening of the scope of the lego.  IP is no longer simply an RTL view but now includes a multitude of design disciplines/domains (e.g. it now includes a software aspect) and the corresponding integration task must resolve these aspects within the fundamental goals of PPA as well as cost.

De Geus built on Tan's answer to highlight that the complexity was pushing the high-level boundaries of software and the physical boundaries of the semiconductor technlogy.  He talked about some power use-case examples and the conversation then moved toward power discussions.

From what I see, growing complexity is a real challange to IP integration. From a pure data perspective - there's a lot more of it, the type of data is changing, it has to be resolved within shorter timeframes and quality cannot be compromized.

Whilst I agree with Segar's challenge of checking that integration it is done correctly and with the  industry straining at the greater challenges in SoC verification complexity, I think we should also keep focused on the challange to strive to integrate correctly in the first place

 

Addressing HW/SW Interface Quality through Standards

As software is an increasingly important aspect of system development, product schedules are mandating the earlier development of software concurrently with hardware. The Hardware/Software (HW/SW) interface is a critical development artifact that plays a key role in efficient system realization.  Here is a white paper presented at DVCON2012 that discusses the typical complexities encountered when designing the SW/HW interactions.

 

DVCON : Accellera and Standards Integration?

As part of Monday's tutorial session, for the second year running,  there was an Accellera 'Town-Hall' meeting where DVCON participants got the chance to ask questions regarding the future of the freshly named Accellera Systems Initiative.  Richard Goering wrote about it here.

The hot topic was of course the merger between Accellera and OSCI to create Accellera Systems Initiative.  One interesting perspective that was pointed out by the forum chair, Stan Krolikoski,  was that there needs to be  work done within  Accellera to integrate the standards.  Krolikoski cited a good example of this with UVM and IP-XACT and how the technical committees worked with each other to help to integrate the standards.   I, with my Duolog colleagues have been very closely involved with this work as we sit on both the VIP-TC as well as the IP-XACT TC and see major benefit in aligning these standards activities.  The IP-XACT specification schema of regsiters was used as a reference when developing the UVM register model and consequently additional UVM requirements were fed back to the IP-XACT TC to be included in the next IP-XACT schema update.

 I presented a slot of the Monday IP-XACT tutorial sessions titled 'IP-XACT and UVM' where I detailed the benefits of utilizing these standards to improve HW/SW interface quality.  I also discussed the need for a more horizontal approach to integrate these vertical standards.  An echo that I hear every year is that there is a new standard, a new model that needs to be supported.  I think this is a central part of EDA evolution but we need to ensure that we evolve these standards not only in their vertical domains but also to make sure that these models can communicate with each other seamlessly across these domains. Interesting enough one of the final questions on the IP-XACT tutorial session was about the linkage, if any between IP-XACT and the UCIS (Unified Coverage Interoperability standard) .  It will be interesting to see who tackles these types of  horizontal integration of standards into the future.

 

That 'IP-XACT and UVM' presentation can be found here: